It is desirable for some types of signals to be implemented with low-skew resources. For example, a designer may wish to implement a clock such that a signal propagating from a source reaches all destinations at approximately the same time. A designer may also wish, for example, to implement an asynchronous clear such that all registers affected by the clear signal are cleared and released at the same time. Modern FPGAs have a variety of low-skew networks available to attempt to address these design needs. These include, for example, chip-level, quadrant-level, and octant-level low-skew networks. Chip-level (or chip-wide) low-skew networks distribute signals with low-skew throughout the entire FPGA. Quadrant-level/octant-level (or local) low-skew networks distribute signals with low-skew throughout smaller areas within an FPGA. Modern FPGA designs, however, place differing demands on low-skew networks available in FPGAs. Some designs heavily utilize chip-level low-skew networks because many high fanout signals (that tend to more naturally cover a large portion of the chip) need to be distributed with low-skew. Other designs heavily utilize octant-level low-skew networks because many low fanout signals (that tend to be highly localized) need to be distributed with low skew. It is more efficient to use these octant-level networks for the low fanout signals, leaving the chip-wide networks for any high fanout signals the designs may have.
Local low-skew networks utilize less silicon area than chip-wide networks. Hence, more low-skew networks can be built cost effectively by creating local networks as opposed to chip-wide networks. This allows a larger number of signals to be distributed with low skew. Local low-skew networks also have the added benefits of imposing a smaller delay on signals and consuming less power than chip-wide networks. However, because local low-skew networks can only distribute signals to a portion of the FPGA chip, placement of elements utilizing these networks needs to be constrained to the smaller area.
Due to silicon area and metal layer costs, the implementation of a large number of chip-wide and local networks is prohibitive. Thus, FPGA manufacturers have had to decide on the number of dedicated chip-wide networks and local networks to offer in an FPGA. However, tailoring the network counts to any particular design may be disadvantageous for other designs.
Thus, what is needed is a low-skew network design that offers the flexibility to satisfy both the needs of designs that heavily utilize chip-wide low-skew networks and the needs of designs that require a larger number of local low-skew networks.